`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:19:56 10/06/2011 
// Design Name: 
// Module Name:    register 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module register5 (in, out, wen, rst, clk);
  parameter n = 5;

  output [n-1:0] out;
  input [n-1:0] in;
  input wen;
  input rst;
  input clk;

  reg [n-1:0] out;

  always @(posedge clk) 
    begin 
      if (rst) 
        out = 0; 
      else if (wen) 
        out = in; 
    end 
endmodule 